Soft-switching voltage-edge-rate-limiting power inverter

ABSTRACT

An auxiliary resonant soft-edge pole inverter circuit is provided. The power inverter circuitry may include a first pair of capacitors in parallel with a corresponding pair of main power switching modules, each power switching module comprising a switch and a diode in parallel and sharing a common central node with the first pair of capacitors. The power inverter circuit may further include a first pair of auxiliary switches connected in series with a first pair of inductors, respectively, to generate resonant current from a DC power source, the first pair of inductors also sharing the common central node. The power inverter circuitry may further include a second pair of auxiliary switches connected in series with a second pair of capacitors, respectively, the second pair of auxiliary switches also sharing the common central node, the circuit producing an alternating current output at the common central node.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional Application No. 62/865,292 filed Jun. 23, 2019, the entirety of which is hereby incorporated by reference.

STATEMENT REGARDING GOVERNMENT FUNDING

This invention was made with government support under DE-EE0005568 awarded by the Department of Energy. The government has certain rights in the invention.

TECHNICAL FIELD

The present application relates to DC-to-AC power inverters, and more specifically, to soft-switching inverters.

BACKGROUND

Switch-mode DC-to-AC inverters are widely used in variable-speed motor drive systems and other applications. To increase switching frequency and reduce switching loss, power switches have been made faster in the past decades. The switching times of insulated-gate bipolar transistors (IGBTs) have reduced to tens of nanoseconds, while those of wide-bandgap (WBG) devices, such as Silicon Carbide and Gallium Nitride devices, have reduced to several nanoseconds.

As switches are made faster, the inverter output voltage edge rate (dv/dt) becomes larger. Various deleterious effects have been experienced and documented since the introduction of IGBTs. These problems include overvoltages at the motor/inverter terminals, electromagnetic interference, large common-mode currents, and the failure of motor bearings due to induced micro-arcs. To reduce the occurrence of problems resulting from high dv/dt, some standards have been established that limit the dv/dt going into motor drives, among which the US National Electrical Manufacturers Association (NEMA) MG1 Part 31 is commonly observed in the US.

Conventional dv/dt-limiting methods include increasing the external gate resistance or Miller capacitance of the switches, and adding a dv/dt filter between the inverter and the motor. All of these methods, especially the dv/dt filter, can effectively reduce the dv/dt but will introduce extra losses, size and weight of the system.

Soft-switching inverters that are originally developed to reduce switching loss can also limit the dv/dt in the circuits. They can possibly replace the dv/dt filter which may result in reduction in total loss and size/weight. Among various soft-switching inverter topologies, the auxiliary resonant commutated pole (ARCP) inverter and its variants are suitable for variable-speed motor drive systems because they have full pulse width modulation (PWM) control capabilities. The original ARCP inverter can realize zero-voltage switching (ZVS) and zero-current switching (ZCS) in its main and auxiliary switches, respectively. However, it has several drawbacks. First, the necessary mid-voltage point requires extra balancing circuits. Secondly, a boost current needs to be generated, which requires accurate current sensing and/or switch triggering, and results in complicated control. Thirdly, the reverse-recovery current of the auxiliary diodes will induce a large voltage across the auxiliary switches. Therefore, snubbers or voltage-clamping circuits are required, which generate extra losses. To eliminate these drawbacks, some variants of the ARCP were proposed over the past decades.

One approach to improve the ARCP is to use a transformer or coupled inductor. A topology described in J. D. Herbst, F. D. Engelkemeir, and A. L. Gattozzi, “High power density and high efficiency converter topologies for electric ships,” in Proc. IEEE Electric Ship Technol. Symp. (ESTS), April 2013, pp. 360-365 uses a 1:1 transformer to create a virtual mid-voltage point, and the auxiliary switches only conduct half of the resonant current. However, the transformer needs to be reset after each switching cycle by extra circuits. A transformer-assisted resonant pole inverter is proposed in X. Yuan and I. Barbi, “Analysis, designing, and experimentation of a transformer-assisted pwm zero-voltage switching pole inverter,” IEEE Trans. Power Electron., vol. 15, no. 1, pp. 72-82, January 2000. Its transformer has a turns ratio different from one so the boost current is not required, which makes control simpler. The transformer current can be properly reset. However, the transformer is bulky and its leakage inductance is part of the resonant inductor which makes parameter design more challenging.

The other approach to improve the ARCP is represented by the auxiliary resonant pole (ARP). The ARP connects the resonant inductor to the upper or lower DC bus through auxiliary switches so it does not need a mid-voltage point. Due to this configuration, the boost current is not required, and the auxiliary switch turn-on and the main switch turn-off can be triggered at the same time, which makes control simpler. In addition, the transient voltage across auxiliary switches is clamped to the DC-bus voltage by auxiliary diodes. However, there are still some drawbacks with the ARP inverter. The auxiliary switches have lossy hard-switched turn-off. In addition, there may be a circulating current in the auxiliary circuits when a main switch module is conducting continuously, which again generates loss. A circuit proposed in W. Yu, J. S. Lai, and S. Y. Park, “An improved zero-voltage switching inverter using two coupled magnetics in one resonant pole,” IEEE Trans. Power Electron., vol. 25, no. 4, pp. 952-961, April 2010 uses two coupled magnetics as resonant inductors so the circulating current can be prevented. However, the turn-off transients of the auxiliary switches are not perfect ZCS because of the remaining magnetizing current. Therefore, improvements are needed in the field.

The active auxiliary edge resonant pole (AAERP) (see M. Nakamura, T. Yamazaki, Y. Fujii, T. Ahmed, and M. Nakaoka, “A novel prototype of auxiliary edge resonant bridge leg link snubber-assisted soft-switching sine-wave PWM inverter,” Elect. Eng. Jpn., vol. 155, no. 4, pp. 64-76, 2006) and the double ARCP (DARCP) (see E. Chu, X. Zhang, and L. Huang, “Research on a novel modulation strategy for double auxiliary resonant commutated pole soft-switching inverter with the shunt dead time,” IEEE Trans. Power Electron., vol. 31, no. 10, pp. 6855-6869, October 2016.) improve upon ARP by adding a second pair of capacitors to realize ZVS turn off in the auxiliary switches. However, the second pair of capacitors may not be precharged to the DC-bus voltage, so the output dv/dt may sometimes be large.

BRIEF DESCRIPTION OF THE DRAWINGS

In the following description and drawings, identical reference numerals have been used, where possible, to designate identical features that are common to the drawings.

FIG. 1 is a schematic and timing diagram illustrating an auxiliary resonant soft-edge pole inverter circuit according to various aspects.

FIG. 2A is a schematic and timing diagram illustrating operation of a power inverter in a diode-to-switch (D2S) commutation during time Interval A according to various aspects.

FIG. 2B is a schematic and timing diagram illustrating operation of a power inverter in a D2S commutation during time Interval B according to various aspects.

FIG. 2C is a schematic and timing diagram illustrating operation of a power inverter in a D2S commutation during time Interval C according to various aspects.

FIG. 2D is a schematic and timing diagram illustrating operation of a power inverter in a D2S commutation during time Interval D according to various aspects.

FIG. 2E is a schematic and timing diagram illustrating operation of a power inverter in a D2S commutation during time Interval E according to various aspects.

FIG. 2F is a schematic and timing diagram illustrating operation of a power inverter in a D2S commutation during time Interval F according to various aspects.

FIG. 2G is a schematic and timing diagram illustrating operation of a power inverter in a D2S commutation during time Interval G according to various aspects.

FIG. 2H is a schematic and timing diagram illustrating operation of a power inverter in a D2S commutation during time Interval H according to various aspects.

FIG. 3A is a schematic and timing diagram illustrating operation of a power inverter in a switch-to-diode (S2D) commutation during time Interval H according to various aspects.

FIG. 3B is a schematic and timing diagram illustrating operation of a power inverter in an S2D commutation during time Interval I according to various aspects.

FIG. 3C is a schematic and timing diagram illustrating operation of a power inverter in an S2D commutation during time Interval J according to various aspects.

FIG. 3D is a schematic and timing diagram illustrating operation of a power inverter in an S2D commutation during time Interval K according to various aspects.

FIG. 3E is a schematic and timing diagram illustrating operation of a power inverter in an S2D commutation during time Interval L according to various aspects.

FIG. 4 is a schematic and timing diagram illustrating operation of a power inverter circuit in a D2S commutation during time Interval C₂ according to various aspects.

FIG. 5A-B are state-plane plots of ARSEP and AAERP according to various aspects.

FIG. 6 is a schematic illustrating an auxiliary resonant soft-edge pole inverter circuit with metal-oxide-semiconductor field-effect transistors (MOSFETs) according to various aspects.

The attached drawings are for purposes of illustration and are not necessarily to scale.

DETAILED DESCRIPTION

In the following description, some aspects will be described in terms that would ordinarily be implemented as software programs. Those skilled in the art will readily recognize that the equivalent of such software can also be constructed in hardware, firmware, or micro-code. Because data-manipulation algorithms and systems are well known, the present description will be directed in particular to algorithms and systems forming part of, or cooperating more directly with, systems and methods described herein. Other aspects of such algorithms and systems, and hardware or software for producing and otherwise processing the signals involved therewith, not specifically shown or described herein, are selected from such systems, algorithms, components, and elements known in the art. Given the systems and methods as described herein, software not specifically shown, suggested, or described herein that is useful for implementation of any aspect is conventional and within the ordinary skill in such arts.

The present disclosure provides a soft-switching circuit to control an inverter output dv/dt with less loss, size and weight than prior-art dv/dt limiting methods, while eliminating the drawbacks of prior-art soft-switching circuits. A circuit topology is provided, referred to herein as an auxiliary resonant soft-edge pole (ARSEP) inverter that realizes soft-switching in all of the main and auxiliary switches and ensures that the inverter dv/dt is limited by circuit parameters. The second pair of resonant capacitors will always be fully pre-charged so the inverter dv/dt can be well-controlled.

One embodiment of a single-phase ARSEP inverter is shown in FIG. 1, in which auxiliary circuits are illustrated using a dashed box. Capacitors C₁ and C₂ are connected in parallel with the main switch modules S₁/D₁ and S₂/D₂. Auxiliary switches S₃ and S₄ are connected in series with inductors L₁ and L₂ to generate resonant current.

It is notable that S₃ and S₄ are unidirectional to prevent circulating current. Capacitors C₃ and C₄ have two roles. When S₅ (S₆) is on, C₃ (C₄) facilitates soft-switching of the main switches; when S₅ (S₆) is off, C₃ (C₄) and D₃ (D₄) serve as the turn-off snubber of S₃ (S₄). Diodes D₅ and D₆ enable pre-charging of C₃ and C₄, which prepares them for the next resonant process so that the dv/dt is well-controlled by circuit parameters. Diodes D₇ and D₈ direct residue energy in L₁ and L₂ back to the power source. It is assumed that C₁=C₂=C_(a), C₃=C₄=C_(b), and L₁=L₂=L. The “+” signs in FIG. 1 define the ports where positive current goes into the devices.

Output Current Jo may be constant during commutation. Since inverter operation is symmetric for positive and negative output current I_(o), without losing generality, the circuit operation with a positive output current (I_(o)>0) will be explained in the following subsections. The output current is generally constant during the commutation because the commutation time is relatively short.

A. Diode-to-Switch Commutation

A commutation in which the output current I_(o) commutes from a diode to a switch is called a diode-to-switch (D2S) commutation.

Interval A (t<t₀): Initially, S₂ is ON while D₂ actually conducts 1A (FIG. 2A). Voltages v_(C1)=E, v_(C2)=0, and v_(C3)=E due to the presence of D₅. In order to demonstrate the basic operation of the circuit, it is assumed that C₄ is initially pre-charged, i.e., v_(C1,0)=E. The situation where v_(C4,0)<E will be discussed further below.

Interval B (t₀≤t<t₁): At t₀, a D2S commutation is commanded. Switch S₂ is turned off while S₃ and S₅ are turned on (FIG. 2B). Since D₂ is conducting, S₂ is turned off with zero-voltage-zero-current switching (ZVZCS). Since i_(L1)(t₀)=0, S₃ is turned on with ZCS. Since v_(C3)(t₀)=E, S₅ is turned on with ZVZCS. Current i_(L1) increases substantially linearly.

Interval C (t₁≤t<t₂): At t₌₁, i_(L1) increases to I_(o) whereupon D₂ stops conducting and L₁ starts to resonate with C₁, C₂, and C₃ (FIG. 2C). Voltage v_(o) increases while v_(C4) stays at E since S₆ is OFF.

Interval D (t₂≤t<t₃): At t₂, v_(o) reaches E and the resonance stops (FIG. 2D). Current i_(L1) supplies I_(o). Since i_(L1)>I_(o), the extra current circulates in the circuit shown in FIG. 2D. Based on simulation and experiment, the extra current circulates in the L₁-D₁-S₃ and L₁-S₅-D₃ loops. The current in the L₁-D₆-D₈-S₃ loop is negligible because there are two diodes in this loop. Ideally, ii is constant and is actually at its peak value

$\begin{matrix} {I_{L\; 1p} = {\frac{E}{Z_{1}} + I_{o}}} & (1) \end{matrix}$ where

$\begin{matrix} {Z_{1} = \sqrt{\frac{L}{{2C_{a}} + C_{b}}}} & (2) \end{matrix}$

Interval E (t₃≤t<t₄): At t₃, S₁ is turned on while S₃ and S₅ are turned off so i_(L1) starts to charge C₃ (FIG. 2E). Since D₁ is conducting, S₁ is turned on with ZVZCS. Since v_(C3)(t₃)=0, S₃ and S₅ are turned off with ZVS. The energy in L₁ at t₃ is

$\begin{matrix} {W_{L1} = {{\frac{1}{2}L_{1}I_{L1p}^{2}} > {{\frac{1}{2}C_{b}E^{2}} + {\frac{1}{2}{LI}_{o}^{2}}}}} & (3) \end{matrix}$ Therefore, L₁ has enough energy to charge C₃ to E.

Interval F (t₄≤t<t₅): At t₄, C₃ is charged to E whereupon D₇ starts to conduct (FIG. 2F). The energy transferred to C₃ is ½C_(b)E², so the energy remains in L₁ is still higher than ½LI_(o) ² according to (3). Therefore, i_(L1)(t₄)>I_(o), so D₁ still conducts current. Current i_(L1) will decrease linearly, and the energy will flow back to the DC source.

Interval G (t₅≤t<t₆): At t₅, i_(L1) decreases to I_(o) while D₁ stops conducting and S₁ starts to conduct (FIG. 2G). Current i_(L1) decreases linearly to zero at t₆, which ends the D2S commutation.

B. Switch-to-Diode Commutation

A commutation in which the output current commutes from a switch to a diode is called a switch-to-diode (S2D) commutation.

Interval H (t₆≤t<t₇): Prior to an S2D commutation, the circuit is in Interval H where S₁ is conducting (FIG. 3A).

Interval I (t₇≤t<t₈): At t₇, an S2D commutation is commanded so S₁ is turned off while S₄ and S₆ are turned on. Inductor L₂ starts to resonate with C₁, C₂, and C₄ (FIG. 3B). Since v_(C1)(t₇)=0, S₁ is turned off with ZVS. Since i_(L2)(t₇)=0, S₄ is turned on with ZCS. Since v_(C4)(t₇)=E, S₆ is turned on with ZVZCS. Voltage v_(o) decreases and v_(C3) stays at E since S₅ is OFF.

Interval J (t₈≤t<t₉): At t₈, v_(o) decreases to zero and i_(L2) starts to circulate in the circuit (FIG. 3C). According to the simulation and experiment, i_(L2) circulates in the L₂-S₄-D₂ and L₂-D₄-S₆ loops. The current in the L₂-S₄-D₇-D₅ loop is negligible. Ideally, i_(L2) is constant and is at its peak value

$\begin{matrix} {I_{L2p} = {\sqrt{I_{o}^{2} + \left( \frac{E}{Z_{1}} \right)^{2}} - I_{o}}} & (4) \end{matrix}$

Interval K (t₉≤t<t₁₀): At t₉, S₂ is turned on while S₄ and S₆ are turned off. Current i_(L2) starts to charge C₄ (FIG. 3D). Since D₂ is conducting, S₂ is turned on with ZVZCS. Since v_(C4)(t₉)==0, S₄ and S₆ are turned off with ZVS. Unlike the D2S commutation, L₂ may not have sufficient energy to charge C₄ up to E. Here, it is assumed that L₂ has sufficient energy so v_(C4) reaches E.

Interval L (t₁₀≤t<t₁₁): At t₁₀, v_(C4) reaches E and D₈ starts to conduct. Current i_(L2) decreases linearly to zero at t₁₁, which completes an S2D commutation.

C. Alternative Mode of Operation

According to (4), I_(L2p) decreases when I_(o) increases. The energy in L₂ in Interval J is

$\begin{matrix} {W_{L2} = {\frac{1}{2}{LI}_{L2p}^{2}}} & (5) \end{matrix}$

It may be less than ½C_(b)E², especially when I_(o) is large or C_(a) is much smaller than C_(b). Therefore, C₄ may not be charged to E even absorbing all energy in L₂. In this case, Interval K ends at t′₁₀ when i_(L2) decreases to zero. The circuit operation will then skip Interval L and goes directly to Interval A. Then, the initial voltage of C₄ for the next D2S commutation v_(C4,0) is less than E. In the next D2S commutation, C₄ stays at v_(C4,0) in Interval B. Interval C will actually have two subintervals denoted by Intervals C₁ and C₂.

Interval C₁ (t₁≤t<t_(1.5)): This interval is similar to Interval C (FIG. 2C) except that v_(C4) stays at v_(C4,0).

Interval C₂ (t_(1.5)≤t<t₂): At t_(1.5), v_(o) increases to v_(C4,0) and D₆ starts to conduct current (FIG. 4). Inductor L₁ starts to resonate with C₁₋₄. When v, increases to E, i_(L1) increases to its peak value

$\begin{matrix} {I_{L\; 1p}^{\prime} = {\sqrt{{\left( \frac{E - v_{{C\; 4},0}}{Z_{3}} \right)^{2}\left( {1 - \frac{Z_{3}^{2}}{Z_{1}^{2}}} \right)} + \left( \frac{E}{Z_{1}} \right)^{2}} + I_{o}}} & (6) \end{matrix}$ where

$\begin{matrix} {Z_{3} = \sqrt{\frac{L}{{2C_{a}} + {2C_{b}}}}} & (7) \end{matrix}$

Since Z₃<Z₁ and I_(L1p)′>I_(L1P), according to (3), L₁ has enough energy to charge C₃ up to E, and the remaining i_(L1) is still greater than I_(o). This interval ends at t₂ when v_(o) increases to E. Voltage v_(C4) increases to E at t₂, which prepares for the next S2D commutation. This pre-charging feature is not available in AAERP or DARCP, so they may result in high dv/dt.

D. Summary of Circuit Operation

The gating signals of the ARSEP inverter can be generated based on the PWM signal and a time delay td, as shown in FIG. 3. The requirement on td is

$\begin{matrix} {{t_{d} > {t_{B} + t_{C}}} = {\frac{I_{o}L}{E} + t_{C}}} & (8) \end{matrix}$ where

$\begin{matrix} {\frac{\pi}{2\omega_{1}} \leq t_{C} < \frac{\pi}{2\omega_{3}}} & (9) \end{matrix}$

$\begin{matrix} {\omega_{1} = \frac{1}{\sqrt{L\left( {{2C_{a}} + C_{b}} \right)}}} & (10) \\ {\omega_{3} = \frac{1}{\sqrt{L\left( {{2C_{a}} + {2C_{b}}} \right)}}} & (11) \end{matrix}$

From (8), td is a function of f₀. The first term depends on circuit parameters, and the second term is mainly determined by allowable dv/dt. Therefore, it is possible to reduce t_(d) through the parameter design to cater to high switching frequencies.

If t_(d) is constant, all gating signals can be generated without any sensing. Then, t_(d) should be longer than the maximum possible voltage commutation time

$\begin{matrix} {t_{c,\max} = {\left( {t_{B} + t_{C}} \right)_{\max} = {\frac{I_{p}L}{E} + \frac{\pi}{2\omega_{3}}}}} & (12) \end{matrix}$

where I_(p) is the peak output current. If I_(o) is measured by a current sensor, a lookup table can be used to determine the required t_(d). Then, the duration of Intervals D and J as well as the associated losses can be reduced without affecting the dv/dt performance.

The circuit operation can be represented in a more concise way using a state-plane plot as shown in FIG. 5A. The two normalized states for the state-plane plot are defined as:

$\begin{matrix} {{\overset{¯}{i} = \frac{iZ_{1}}{E}},{\overset{¯}{v} = \frac{v}{E}}} & (13) \end{matrix}$

The moving directions of the state are indicated by arrows. From t₁ to t_(1.5), the state follows a circular arc about the center (1, Ī_(o)) with a rotational speed of ω₁. Similarly, from t₇ to t₈, the state follows another circular arc about the center (0, Ī₀) with the same speed ω₁. If v_(C4,0)=E, from Point P, the state will keep following the solid circular arc to Point Q. If v_(C4,0)<E, from Point P, the state follows the dashed curve and goes to Point R.

The state-plane plot of AAERP is shown in FIG. 5B. When C₃ and C₄ are fully charged, the state follows the solid line to Point Q. However, when C₃ or C₄ is lightly charged (which is likely when I_(o) is large), the state moves from the origin to Point P and then to Point R, during which high dv/dt will occur. DARCP suffers a similar problem. ARSEP solves the problem by pre-charging C₃ (C₄) through diode D₅ (D₆) so that dv/dt can be well controlled by circuit parameters.

E. Voltage and Current Characteristics

The peak inductor current, di/dt, and dv/dt in the ARSEP inverter can be derived as:

$\begin{matrix} {I_{L,\max} = {{\frac{E}{Z_{3}} + I_{p}} = {\left( {\frac{1}{{\overset{¯}{Z}}_{3}} + 1} \right)I_{p}}}} & (14) \\ {\frac{di_{L}}{{dt}_{\max}} = \frac{E}{L}} & (15) \\ {\frac{dv_{o}}{{dt}_{\max}} = \frac{{0.8}E\omega_{1}}{\Delta{\theta_{T2D}\left( {\overset{¯}{Z}}_{1} \right)}}} & (16) \end{matrix}$ where

$\begin{matrix} {{\Delta{\theta_{S2D}\left( {\overset{¯}{Z}}_{1} \right)}} = {{\cos^{- 1}\frac{0.1}{\sqrt{{\overset{¯}{Z}}_{1}^{2} + 1}}} - {\cos^{- 1}\frac{0.9}{\sqrt{{\overset{¯}{Z}}_{1}^{2} + 1}}}}} & (17) \end{matrix}$ is the angle being swept when v _(o) decreases from 0.9 to 0.1, as shown in FIG. 5A, because dv/dt defined by the NEMA MG-1 standard is the average voltage-change rate when the voltage changes between 10% and 90%. The normalized impedance is defined as

$\begin{matrix} {\overset{¯}{Z} = \frac{I_{p}Z}{E}} & (18) \end{matrix}$

F. Example Table 1—ARSEP Inverter Design Specification (Example)

Item Value DC-bus voltage, E 200 V  Peak output current, I_(p) 20 A  Maximum voltage edge rate, dv/dt_(limit)  200 V/μs Maximum current edge rate, di/dt_(limit)   50 A/μs Maximum inductor current, I_(L,limit) 50 A  Switching frequency, f_(sw)  10 kHz Maximum commutation time 5 μs

By way of example, given the specifications in Table 1, an ARSEP inverter may be designed as follows. Referring to (14)

$\begin{matrix} {{{\overset{¯}{Z}}_{3} > \frac{I_{p}}{I_{L,{limit}} - I_{p}}} = {{0.6}7}} & (19) \end{matrix}$

It is selected that Z ₃=1 to limit the maximum inductor current. Based on (2) and (7), it can be concluded that Z₁>Z₃, so it is selected that Z ₁=1.1. Subsequently, according to (16) and (17) Δθ_(S2D)=0.583 rad  (20)

$\begin{matrix} {\omega_{1} = {\frac{\frac{dv}{{dt}_{limit}}\;{\Delta\theta}_{S2D}}{0.8E} = {{0.7}29\mspace{14mu}{{rad}/{\mu s}}}}} & (21) \end{matrix}$

Based on Z ₁, Z ₃, and ω₁, the values of the resonant components are calculated to be L=15 μH, C_(a)=50 nF, and C_(b)=25 nF. In order to maximize the benefit of soft switching, C_(b) should be large enough so that S₃ and S₄ are over-snubbed. With this design, according to (12) and (14)-(16), t_(cmax)=3.9 μs, I_(Lmax)=40 A, di_(L)/dt_(max)=13.3 A/μs, and dv_(o)/dt_(max)=200 V/μs, which satisfy NEMA standards.

FIG. 6 illustrates an example of the circuit. The switches may be include metal-oxide-semiconductor field-effect transistors (MOSFETs) (as shown in FIG. 6), an insulated-gate bipolar junction transistor (IGBT), or other suitable transistor. When the switches labelled S₃ and S₄ are MOSFET devices, there are diodes in series with the MOSFET “switch” (labeled D₉ and D₁₀ in FIG. 6), since the unidirectional switches S₃ and S₄ should conduct current in one direction only.

The presently disclosed ARSEP circuit may be implemented to control power inverters in hybrid and electric vehicles, aircraft actuators, ship propulsion, and grid integration of renewable energy sources, or other applications.

In various aspects and examples, the auxiliary resonant soft-edge pole inverter circuit may include a first pair of capacitors (C₁ and C₂) in parallel with a corresponding pair of main power switching modules, each power switching module comprising a switch (S₁/S₂) and a diode (D₁/D₂) in parallel and sharing a common central node with the first pair of capacitors.

The auxiliary resonant soft-edge pole inverter circuit may further include a first pair of auxiliary switches (S₃ and S₄) connected in series with a first pair of inductors (L₁ and L₂) to generate resonant current from a DC power source (E), the first pair of inductors also sharing the common central node.

The auxiliary resonant soft-edge pole inverter circuit may further include a second pair of auxiliary switches (S₅ and S₆) connected in series with a second pair of capacitors (C₃ and C₄). The second pair of auxiliary switches (S₅ and S₆) also sharing the common central node, the circuit producing an alternating current output at the common central node.

The auxiliary resonant soft-edge pole inverter circuit may further include a second pair of diodes (D₃ and D₄) connected between the second pair of auxiliary switches (S₅ and S₆) and the inductors (L₁ and L₂).

The auxiliary resonant soft-edge pole inverter circuit may further include a third pair of diodes (D₅ and D₆) connected in parallel with the second set of auxiliary switches (S₅ and S₆) and sharing the common central node.

The auxiliary resonant soft-edge pole inverter circuit may further include a fourth pair of diodes (D₇ and D₉) connected between the second pair of auxiliary switches (S₃ and S₄) and the DC power source (E).

The auxiliary resonant soft-edge pole inverter circuit may further include a fifth pair of diodes (D₉ and D₁₀) respectively connected in series with the second pair of auxiliary switches (S₃ and S₄).

In various aspects and examples, the power inverter may include a plurality of capacitors comprising a first capacitor C₁, a second capacitor C₂, a third capacitor C₃, and a fourth capacitor C₄. The power inverter may further include a plurality of switches. The switches may include a first switch S₁, a second switch S₂, a third switch S₃, a fourth switch S₄, a fifth switch S₅, and a sixth switch S₆. The power inverter may include a plurality of inductors. The inductors may include a first inductor L₁ and a second inductor L₂. The power inverter may further include a plurality of diodes comprising a first diode D₁ and a second diode D₂.

The first switch S₁ may be connected in parallel with the first capacitor C₁ and the first diode D₁. The second switch S₂ may be connected in parallel with a second capacitor C₂ and a second diode D₂.

The third switch S₃ may be connected in series with the first inductor L₁. The fourth switch S₄ may be connected in series with the second inductor L₂.

The fifth switch S₅ may be connected in series with the third capacitor C₃ and the sixth switch S₆ may be connected in series with the fourth capacitor C₄.

The first switch S₁, the second switch S₂, the first diode D₁, the second diode D₂, the first capacitor C₁, the second capacitor C₂, the first inductor L₁, the second inductor L₂, and the fifth switch S₅ and the sixth switch S₆ may share a common node.

In some examples, the diodes further comprise third diode D₃ and fourth diode D₄. The third diode D₃ may be connected between the third switch S₃ and the first inductor L₁. The fourth diode D₄ may be connected between the second inductor L₂ and the fourth switch S₄.

In some examples, the diodes may further include a fifth diode D₅ and sixth diode D₆. The fifth diode D₅ may be connected in parallel with the fifth switch S₅ and the sixth diode D₆ may be connected in parallel with the sixth switch S₆. Further, the fifth diode D₅ and the sixth diode D₆ may both connect to the common node.

In some examples, the diodes may include a seventh diode D₇ and an eight diode D₈. The seventh diode D₇ may be connected between the fourth switch S₄ and a DC power source E. The eight diode D₈ may be connected between the third switch S₃ and the DC power source E.

In some examples, the third switch S₃ and the fourth switch S₄ may include MOSFETs. In such examples, the diodes may further include a diode D₉ and a diode D₁₀. The diode D₉ may be connected in series with the third switch in S₃. The diode D₁₀ may be connected in series with the fourth switch in S₄. Alternatively or in addition, the power inverter may include switch circuitry (identified as 602 and 604 in FIG. 6). The switch circuitry may include a series connection of a diode and a MOSFET.

The invention is inclusive of combinations of the aspects described herein. References to “a particular aspect” and the like refer to features that are present in at least one aspect of the invention. Separate references to “an aspect” (or “embodiment”) or “particular aspects” or the like do not necessarily refer to the same aspect or aspects; however, such aspects are not mutually exclusive, unless so indicated or as are readily apparent to one of skill in the art. The use of singular or plural in referring to “method” or “methods” and the like is not limiting. The word “or” is used in this disclosure in a non-exclusive sense, unless otherwise explicitly noted.

The invention has been described in detail with particular reference to certain preferred aspects thereof, but it will be understood that variations, combinations, and modifications can be effected by a person of ordinary skill in the art within the spirit and scope of the invention. 

The invention claimed is:
 1. An auxiliary resonant soft-edge pole inverter circuit, comprising: a first pair of capacitors connected in parallel with a corresponding pair of main power switching modules, each power switching module comprising a switch and a diode in parallel and sharing a common central node with the first pair of capacitors; a first pair of auxiliary switches directly connected in series with a first pair of inductors, respectively, to generate resonant current from a DC power source, the first pair of inductors also sharing the common central node; a second pair of auxiliary switches directly connected in series with a second pair of capacitors, respectively, the second pair of auxiliary switches also sharing the common central node, the auxiliary resonant soft-edge pole inverter circuit producing an alternating current output at the common central node; a second pair of diodes connected between the second pair of auxiliary switches and the first pair of inductors, respectively; a third pair of diodes connected in parallel with the second pair of auxiliary switches, respectively, and directly connected to the common central node; a fourth pair of diodes directly connected between the second pair of auxiliary switches and the DC power source, respectively; and a fifth pair of diodes directly connected in series with the first pair of auxiliary switches, respectively.
 2. The auxiliary resonant soft-edge pole inverter circuit of claim 1, wherein at least one switch among the first pair of the switches and the second pair of switches comprises an insulated-gate bipolar transistor.
 3. The auxiliary resonant soft-edge pole inverter circuit of claim 1, wherein at least one switch among the first pair of the switches and the second pair of switches comprise a metal-oxide-semiconductor field-effect transistor (MOSFET).
 4. A power inverter circuit, comprising: a plurality of capacitors comprising a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor; a plurality of switches comprising a first switch, a second switch, a third switch, a fourth switch, a fifth switch, and a sixth switch; a plurality of inductors comprising a first inductor and a second inductor; and a plurality of diodes comprising a first diode, a second diode, a third diode, a fourth diode, a fifth diode, a sixth diode, a seventh diode, an eight diode, a ninth diode, and a tenth diode, wherein the first switch is connected in parallel with the first capacitor and the first diode, and the second switch is connected in parallel with the second capacitor and the second diode, wherein the third switch is directly connected in series with the first inductor and the fourth switch is directly connected in series with the second inductor, wherein the fifth switch is directly connected in series with the third capacitor and the sixth switch is directly connected in series with the fourth capacitor, wherein the first and second switches, the first and second diodes, the first and second capacitors, the first and second inductors, and the fifth and sixth switches share a common node, wherein the third diode is connected between the third switch and the first inductor, and the fourth diode is connected between the second inductor and the fourth switch, wherein the fifth diode is connected in parallel with the fifth switch and the sixth diode connected in parallel with the sixth switch, the fifth and sixth diodes both directly connected to the common node, wherein the seventh diode is directly connected between the fourth switch and a DC power source, and the eighth diode is directly connected between the third switch and the DC power source, and wherein the ninth diode is directly connected in series with the third switch, and the tenth diode is directly connected in series with the fourth switch.
 5. The power inverter circuit of claim 4, wherein at least one of the plurality of switches comprises an insulated-gate bipolar switches.
 6. The power inverter circuit of claim 4, wherein at least one of the plurality of switches comprise a metal-oxide-semiconductor field-effect transistor (MOSFET). 